IRC Logs for #circuits Thursday, 2013-01-10

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marky1991prologic, If I fire one event, which triggers more events down the line, those child events are guaranteed to be handled before any event fired after the original event, correct?18:58
marky1991To say it a differnet way: I have two toplevel events. All children events of the first toplevel event are guaranteed to be handled before the second toplevel event18:59
marky1991Because I'm not getting that behavior and I don't know why18:59
prologicnot necessarily18:59
prologicit depends18:59
prologica queue is however used18:59
prologicFIFO18:59
marky1991My file is getting opened after a write event is triggered18:59
prologicthen something else is wrong19:00
prologicin general you can guarantee order of events19:00
prologicbut not necessarily19:00
prologicit depends on a number of things19:00
prologiceg: whether they're occurring simultaneously in three or processes, etc19:00
prologicin this case probably not :)19:00
prologicbut remember you can wait for events to occur as well19:00
prologicusing self.wait19:00
marky1991Hmm. I'll have to studfy more as to why it's doing i tin the right order19:01
jgiorgidown one level (ie parent then child events) in a single process that should be the behavior19:01
prologicor synchronsouly call an event with self.call19:01
jgiorgibut it gets murky if your child events fire more events19:01
marky1991But your file doesn't use wait and it works proprely19:01
marky1991I assume, anywya19:01
prologicmarky1991:  Debugger() is your friend19:01
marky1991I'm using debugger19:01
prologicit does work perfectly -this is true19:01
marky1991I'm doing Register->ready->open, followed by a write19:01
prologicso I'd say you're doing something wrong somewhere19:01
marky1991hmmmmmmm19:02
marky1991Alright19:02
prologicmarky1991:  you probably want to queue up write requests then19:02
marky1991I'll just keep looking then19:02
prologicand only write once everything is ready19:02
prologicthis is in general how File (UNIX) works19:02
marky1991How does the original file avoid doing this?19:02
prologicwrites and their data are queued up in a buffer19:02
prologicand only written out when the underlying file descriptor is ready19:02
prologicie: a _write event has been triggered by the poller19:02
marky1991I could just avoid the ready completely and fire the open in the init function19:03
prologicbut in this case you have to use win32 apis19:03
marky1991I only really seperated it to imitate the original file19:03
prologicbut you should be aiming for similar behavior I think19:03
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jgiorgiprologic: http://delta.justingiorgi.com/static/?name=c17c0089c3a5419a287776191656e561809b909d&content=jpeg19:58
jgiorgiERROR: (<type 'exceptions.TypeError'>) create() got multiple values for keyword argument 'name'19:58
jgiorgiim clueless, i see only one value, unless it's splitting on the numerics20:00
prologicjgiorgi:  show me that request handler's code please20:20
jgiorgiprologic: http://circuits.codepad.org/koheHUSq20:26
jgiorginot much to it20:26
prologicis the result of a form upload?20:28
jgiorgino, url encode20:28
prologicso this is just s straight URL get?20:29
prologicokay20:29
jgiorgiyep20:29
prologiccan you help debug this?20:29
prologicusing pdb or pudb?20:29
prologicI find this strange20:30
prologicshould be easy to fix though20:30
prologicbutI"m surprised20:30
jgiorgiyeah i cant figure it out20:30
jgiorgibecause im only passing one name, and similar handles work20:30
jgiorgihandlers*20:30
jgiorgiis name reserved or used somewhere by circuits.web or something?20:31
prologichmm20:31
prologicare you *sure* you're only passing one name though?20:32
prologiccan you debug the request data you're getting20:32
jgiorgipositive, i curl'ed it so there was nothing there20:32
jgiorgiworks perfectly when i replace "name" with "get"20:34
jgiorgiso name has to be somewhere20:35
prologicok20:36
prologichere's what we'll do20:36
prologicit'l be fixed by tonight when I get home20:36
prologicbut can you please put this into a test case20:36
prologicthat fails every time20:36
prologiccopy one of our tests/web/ tests20:36
jgiorgihrmm, i'll give it a shot20:37
jgiorgihaven't written any tests w/circuits.web except running the methods manually20:38
jgiorgiit's not a big deal now that i figured it out and changed the argument name20:41
jgiorgii gotta sign off, it's 9 and i've been coding for 11 hours20:46
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marky1991prologic, What's with the bare init function in file.py? Why not the normal __init__?21:30
prologicahh21:31
prologicglad you asked21:31
prologicI/We (whatever)21:31
prologicdecided in our infinite wisdom that we'd like a better init21:31
prologicone in which you don't have to remember to do:21:32
prologicsuper(Foo, self).__init__(...)21:32
prologicso hence init21:32
marky1991so you're just automatically calling the BaseComponent __init__ and then call the subclass' init during registration?21:32
prologichowever if you subclass a base component that uses init and you customize it, you're back in the same problem where you have to remember to call the super one :)21:32
prologicno21:33
prologiceven more simpler than that21:33
prologicyou don't have to use it obviously21:33
prologicit's just convenient21:33
prologicand well I like convenience sometimes21:33
prologicalso the reason we overrode a few operators that made sense in circuits21:33
prologiceg:21:33
marky1991ah, yes, i see it there now21:33
prologicm = Manager()21:33
prologicm += Debugger()21:33
marky1991misremembered where the ints were claled21:34
prologicm.run()21:34
prologicit's nothing magical21:34
prologicjust called during __init__21:34
marky1991PS: That is <i>exactly</i> the kind of overloading that makes java ban all of it21:34
marky1991: P21:34
prologicbut after the component has been properly initialized21:34
prologichaha21:34
prologiclook operator overloading is nice21:34
prologicwhen it makes sense to do so21:34
marky1991yeah, I agree21:35
prologicin circuits you really are adding components together to create a component graph21:35
prologicso:21:35
prologicm += Debugger()21:35
marky1991yes, it makes sense if you think about it that way21:35
prologicis effectively iidentical to:21:35
prologicDebugger().register(m)21:35
prologicand they are translated as such21:35
prologicwe also designed the operators to make mathematical sense too21:35
prologicso you can do:21:35
prologicsystem = (Server(8000) + Root())21:35
prologicsystem.run()21:36
prologicor:21:36
prologicself.poller = Select().register(self)21:36
prologicand self.poller is a reference to the Select component21:36
marky1991oh, speaking of pollers21:36
marky1991I think I saw that the select poller is somehow being attached to my file21:36
marky1991should I be concerned about that?21:36
prologichmm21:37
prologicthat should not happen21:37
marky1991k21:37
prologicunless you've subclassed File?21:37
marky1991no, I havenm't21:37
prologicgetting a poller into the system is done through registration (as it anything)21:37
marky1991I'm working on making my file inherit from the original file thoughj21:37
prologicand with File and any socket component21:37
prologicwe normally do it through the registered handler21:37
prologicie:21:37
prologiclook for an existing poller and use that21:37
prologicotherwise register a default one21:38
prologicahhh21:38
prologicyou are subclassing then21:38
prologicinherit == subclassing21:38
prologicin that case21:38
prologicoverride the handlers21:38
marky1991I was planning on just using File as my base21:38
marky1991and override what doesn't make sense21:38
prologic@handler("registered", override=True)21:38
marky1991I satarted to make aBaseFile class, b ut it didnd't make much sense21:38
marky1991oh, you have to specify an override21:38
marky1991I need to relook at the handler decorator21:38
prologicyou do if you want extra stuff21:39
prologicI think it's override=True21:39
prologiccheck the docs for handler21:39
marky1991okie doke21:39
prologicotherwise I'd say use a filter21:39
prologicbut a filter doesn't make sense in a subclassed component21:39
marky1991filter?21:39
prologica handler with filter=True allows you to prevent other handlers from handling the event21:40
prologicif a previous handler returned a True-like object21:40
prologicor an object that evaluated to True21:40
prologicwe use filters all the time!21:40
marky1991If I override File, will the original File handlers be called?21:40
prologicno21:40
marky1991good.21:40
prologicit will be overridden21:40
prologicthe reason the original one gets called21:40
prologicis when you subclass a component21:40
prologicwe inherit the base handlers as well21:41
prologicunless you specify overdie=True21:41
marky1991base handlers?21:41
prologicie: circuits has event handler inheritance21:41
marky1991right21:41
marky1991os any handler I don't specify is inherited21:41
marky1991like normal21:41
prologicas I've said before21:41
prologicdon't think of event handlers as methods21:41
prologicthey're not :)21:41
prologicyes21:42
prologicfor example:21:42
prologicsay you had two components21:42
prologicBase21:42
prologic|-Foo21:42
prologicboth of which had a "hello" handler21:42
prologicif you fired a Hello event21:42
prologicyou would get two results21:42
marky1991oooooh21:42
prologicunless the "hello" handler in Foo was specified with @handler("hello", override=True)21:42
marky1991So the base handler <i>does</i> still get called21:43
prologicunder normal circumstances however21:43
prologicyou should not be subclassing21:43
prologicbut rather using simpler components21:43
prologicie: build complex components from simpler ones21:43
prologicbut I think it's okay here :)21:43
marky1991I could just make a baseFile instead then21:43
prologicthis is how circuits.web is all built21:43
prologicnot a single subclass used in circuits.web afaik21:43
marky1991I was just thinking of everything with normal OOP21:43
prologicall registered components21:43
marky1991but if I do it the current way there'll be override=True s everywhere21:44
prologicwell21:44
prologicyou could do some similar to Python 321:44
prologicin that you create a BaseIO component21:44
marky1991yeah, that's what i'll do21:44
prologicwhere File and your WindowsFile both registered this21:44
prologicthat would actually be really nice I think21:44
marky1991I wasn't going to do it htat way since BaseFile didn't have much to it21:44
prologicand put all the base event handlers in BaseIO21:44
marky1991but having all of them with override=True sounds ugly21:45
marky1991so that's what I'll do21:45
prologic*nods*21:45
prologicperfect :)21:45
prologicyeah21:45
prologicOOP is used to a certain extent in circuits21:45
prologicand in any circuits application21:45
prologic-however- single inheritance is preferred and components21:45
prologicin theory - circuits and any circuits app could run on say tinypy21:46
prologicwhich is an embedded implementation of python but only supports single inheritance21:46
marky1991yeah, i've heard of i21:46
marky1991never used it though21:46
marky1991I even know the original developer21:46
prologicwe may actually officially support tinypy at some point21:46
prologicjust because we can :)21:46
prologicie: run it on a raspbeerrypi21:46
prologicor other smaller embedded devices21:46
prologicI'm glad you're enjoying circuits :)21:47
marky1991it's the prettiest-to-use networking library from what i could see21:47
prologiccompoents, events, event handlers21:47
marky1991twisted and the other one was ugly21:47
prologicand most importantly, how these all talk together in a loosely coupled fashion21:47
marky1991plus, my game uses events21:47
prologic:)21:48
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